1. Field of the Invention
The present invention relates generally to phase locked loop circuit and, more particularly, to a phase locked loop circuit suitable for use in extracting a bit clock signal from a signal reproduced by a rotary head of, for example, a digital audio tape recorder.
2. Description of the Prior Art
Rotary head type digital audio tape recorders have been used so far to record an audio signal on a magnetic tape at high recording density.
The digital audio tape recorder is referred to as a DAT for simplicity and records incoming audio data on a magnetic type wrapped around a rotary drum at a predetermined wrapping angle by rotary heads mounted on the rotary drum and/or reproduces recorded audio data from the magnetic tape by the rotary heads.
When predetermined digital audio data is reproduced from a reproduced signal provided by the rotary heads of the tape recording and/or reproducing apparatus such as the digital audio tape recorder and the like, a bit extracting clock signal (i.e., so-called bit clock signal) is needed. In order to obtain a bit clock signal synchronized with the reproduced signal, a clock reproducing circuit of a phase locked loop (PLL) circuit arrangement has been employed.
When a magnetic tape in which predetermined digital audio data are recorded according to the DAT format is reproduced, a rate (i.e., read-out rate) in which the reproduced signal is read out from the magnetic tape by the rotary heads can be freely determined from a principle standpoint.
Therefore, by switching the revolution rate of the rotary drum while the running speed of the magnetic tape is being kept constant, it is possible to reproduce recorded digital audio data at two read out rates. These rates are a normal speed mode in which the relative speed between the magnetic tape and the rotary head is 3.133 meters/second and half speed mode in which the relative speed is 1.567 meters/second.
When the frequency bands of the reproduced signals in the read out rate of the normal speed mode and in the read out rate in the half speed mode are compared with each other, the frequency band of 9.4 MHz is provided by the read out rate of the normal speed mode, while the frequency band of 4.7 MHz, which is 1/2 that of the former frequency band, is provided by the read out rate of the half speed mode.
Accordingly, while the frequency of the bit clock signal involved in the reproduced signal (the so-called transmission rate of the reproduced signal) becomes 9.4 MHz according to the normal speed mode read out rate, the frequency of 4.7 MHz, which is 1/2 that of the former frequency, is provided according to the half speed mode read out rate.
If bit clock signals are extracted from the reproduced signals having transmission rates which are different by a factor of two by using the same clock reproducing circuit, it is frequently observed that a so-called quasi-locked or pseudo-locked condition occurs in the PLL circuit forming the clock reproducing circuit. Broadly speaking, such a pseudo-locked condition tends to occur when the frequencies of the reproduced signal as the input digital signal and of the clock signal as the output digital signal are placed in a simple integer relationship.
If the pseudo-locked condition occurs, then the clock signal of 4.7 MHz will be transmitted even though the reproduced signal is reproduced at the normal speed read out rate or the clock signal of 9.4 MHz will be transmitted while the reproduced signal is reproduced at the half speed mode read out rate. As a result, the bit of the reproduced signal can not be correctly extracted by a digital signal processing circuit provided at the later stage. Then, the problem is presented that digital audio data involved in the reproduced signal can not be reproduced correctly.